A static random access memory (SRAM) is a significant memory device due to its high speed, low power consumption, and simple operation. Unlike a dynamic random access memory (DRAM) cell, the SRAM does not need to regularly refresh the stored data and it has a straightforward design.
As shown in FIG. 1, each bit in a typical six-transistor SRAM (6T-SRAM) cell 10 is stored on four transistors, generally referred to as load transistors (or pull-up transistors) P1, P2 and driver transistors (or pull-down transistors) N1, N4, that form a flip-flop circuit containing a balanced pair of cross coupled inverters storing a single data bit. This storage cell has two stable states which are used to denote bits 0 and 1. Two additional access transistors (or pass-gate transistors) N2, N3 serve to control the access to a storage cell during read and write operations. Particularly, the pair of pass gates (e.g., a balanced pair of FETs) selectively connect the complementary outputs of the cross coupled inverter to a corresponding complementary pair of bit lines (blc, blt). A word line (WL) connected to the gates of the pass gate FETs N2, N3 selects connecting the cell to the corresponding complementary pair of bit lines.
To function properly, the SRAM cell, when charged, must hold a voltage level, either high (logic 1) or low (logic 0). When reading data from the cell, the cell current generated as the pass-gate transistor turns ‘on’ must not flip the voltage level at the internal cell nodes 11 and 12. To stabilize the cell, the driver or pull-down transistor is fabricated to have a higher conductance than the pass-gate transistor so that the internal node which stores logic ‘0’ will be held low by the strong pull-down transistor.
It is known that the 6T SRAM cell 10 of FIG. 1 suffers a stability problem that is associated with a “Half-Select” operating mode. In the “Half-Select” operating mode, a Row is selected while a Column is not, i.e., the Wordline (WL) is on and one or more of the Bitline pairs is clamped to a supply or reference voltage (e.g., VDD) as indicated (blt=1, blc=1).
Accessing a bit(s) for a read or a write operation from an SRAM array entails driving one of the word lines, turning on the pass gates for one or more cells on that word line. With the pass gates on for that selected word line, the cross-coupled cell inverters are coupled to the corresponding bit line pairs, partially selecting the cells (half selected) on that word line. Selection of one of the columns selects the cell on that word line, the bits actually being accessed. The remaining (M−1) by K bits remain half selected during the access.
During a read, each cell on the selected word line couples its contents to its corresponding bit line pair such that each of the bit line pairs may rise/droop, usually, only to develop a small difference signal (e.g., 50 mV). While the bit line pairs in the selected columns are unclamped and coupled to a sense amplifier, the half selected cells remain clamped together and to the reference voltage. At some point after sensing data for the selected bits, the word line returns low again, deselecting/isolating the cells on that word line. As long as the word line remains high, however, pass gates in half selected cells couple the reference voltage onto both storage nodes in each half selected cell. Depending upon the length of time that the word line remains high, the pass gates couple the partially selected cells tend toward an equilibrium point with the outputs of both of the cross coupled inverters (i.e., the storage nodes) being pulled toward a common voltage. This is normally a measure of cell stability, i.e., selecting the cell and clamping the bit lines to a voltage and noting the point at which the cell becomes meta-stable or switches, i.e., is upset. Unfortunately, imbalances in cell devices can upset half selected cells or at the very least to become meta-stable at normal design voltages. This instability is intolerable.
One solution that attempts to address the 6T SRAM cell stability problem include: 1) applying an offset VDD to the array and a peripheral. While this may sacrifice the array performance, e.g., write performance, the solution can only relieve the stability problem but cannot solve the Half-select problem; and, 2) Using an inverter to control the Column and Row select. FIG. 2 particularly depicts this prior art solution whereby an inverter device 15 comprising two added transistors T1 and T2 receive both the column select (CSC) and wordline (WL) voltage signals.
One problem with this approach is that a floating inverter output (w/e) when both CS and WL are both “0” as seen from the truth table of Table 1. The floating node causes the pass-gates to leak during the time the cell is not selected. This will interfere with selected cell sensing signal.
TABLE 1CSCWLwleOperation00UnknownCol sel Row unsel011Col/Row sel100Col/Row unsel110Col unsel Row sel
It would be highly desirable to provide a semiconductor SRAM cell structure designed to prevent the half-select mode phenomena for increased cell stability.